The present invention relates to a signal generating device for a charge pump for an integrated circuit and to an integrated circuit which comprises such a signal generating device.
In order, in an integrated circuit and, in particular, a semiconductor memory device or DRAM, to generate voltages which, in respect of magnitude, are higher than the supply voltage or are negative, so-called charge pumps are integrated. Charge pumps make it possible to generate multiples and sums of internal voltages. For this purpose, it is necessary to connect the charge pumps to ring oscillators which provide corresponding frequencies from which are derived control signals which are co-ordinated precisely with respect to time. In certain ranges, the maximum possible output current of the charge pumps is proportional to the oscillator frequency. This means that, in standby operation, i.e. with only a low current requirement, it becomes possible, for power loss reasons, to operate the pumps with lower frequencies than in the active operating mode, in which there is a higher current requirement.
Oscillator devices or arrangements which can generate the required control signals for a charge pump are known.
Such an oscillator arrangement according to the prior art is shown in FIG. 4. A signal with a first frequency f1 is generated in a first ring oscillator 110. A second signal with a frequency f2 is generated in a second ring oscillator 112. In this case, the frequency f2 is different from the frequency f1. The two signals generated are fed to a multiplexer 114, by means of which a selection device 116 can select which of the two signals is output by the multiplexer 114.
The signal output by the multiplexer is fed to a delay chain 118, which generates the control signals for a charge pump 120.
In the delay chain 118, the signal received from the multiplexer 114 is delayed by a predetermined delay duration. The delayed signal is in turn delayed by the predetermined delay duration. This process is repeated until the required number of control signals has been obtained. The signals thus obtained are output to a control signal generating unit 122, which generates control signals for the charge pump 120.
This oscillator arrangement of the prior art has the disadvantage, however, that the control signals are inadequately adapted for the charge pump, which leads to an impairment of the efficiency.
Consequently, it is an object of the present invention to provide a signal generating device for a charge pump for an integrated circuit and an integrated circuit which enable an improved efficiency during the operation of the charge pump.
The invention provides a signal generating device for a charge pump for an integrated circuit, in which case the signal generating device has N signal outputs D1, . . . , DN and a signal setting input for setting a frequency f and is designed in such a way that
a periodic signal Sx(t) can be output via the signal output Dx,
all the signals S1(t), . . . , SN(t) have the same settable frequency f, in which case
the following holds true for the signal Sx(t), where 2xe2x89xa6xxe2x89xa6N,
Sx(t)=S1(txe2x88x92(xxe2x88x921)xc2x7xcex94Txxe2x88x92kx/(2f)),
in which case
xcex94Tx is the delay duration of the signal Sx(t) with respect to Sxxe2x88x921(t), and
kx xcex5{0; 1},
the delay duration xcex94tx is dependent on the frequency f.
The frequency f is preferably the inverse of the period duration of the periodic signal Sx(t). Furthermore, the signal generating device is preferably designed in such a way that all the signals Sx(t) for 2xe2x89xa6xxe2x89xa6N satisfy the equation specified above. The delay duration xcex94Tx is preferably inversely proportional to the frequency f. In particular, it is preferred for the delay duration xcex94Tx to increase, the lower the frequency f is.
By virtue of the fact that the delay duration xcex94Tx is dependent on the frequency f, it is possible to ensure that the control signals for the charge pump are in an optimal temporal relationship with one another and the charge pump can thus be operated in an advantageous state for all frequencies.
The signals Sx(t) output all have the same frequency f. Consequently, the temporal sequence of the pulse signals output is the same; in particular, the edges of the signals are spaced apart from one another by the same delay time. However, in a preferred embodiment, it may be provided that the amplitude and/or an offset or a shift of one or more signals is provided.
Preferably, kx=(1+(xe2x88x921)x)/2. Consequently, in each case successive signals are inverted with respect to one another.
The delay duration xcex94Tx is preferably essentially identical, to be precise equal to xcex94T, for all the signals S2(t), . . . , SN(t).
In a preferred embodiment, the signal generating device comprises a multiplicity of oscillator stages connected in ring form, in which case
the oscillator stages each have an oscillator stage input and an oscillator stage output;
in which case the oscillator stage output is respectively signal-connected to the oscillator stage input of the downstream oscillator stage; and
the signal outputs D1, . . . , DN are signal-connected to a respective oscillator stage output of the oscillator stages.
Each oscillator stage preferably has a setting input which is signal-connected to the signal setting input.
By tapping off the signals S1, . . . , SN directly at the oscillator stage outputs, it is possible to obtain the delayed signals directly from the ring oscillator which is used for generating the signal. Consequently, the delay chain which was provided in the prior art can be dispensed with. Furthermore, the multiplexer can likewise be dispensed with since the frequency of the signal generating device according to the invention is variable, and, consequently, only one ring oscillator is required.
Preferably, the oscillator stages each comprise a settable delay element for setting a delay element duration xcfx84VG.
The delay element duration xcfx84VG forms part of the delay duration xcex94Tx.
Preferably, the settable delay element is of capacitive design. It is further preferred that the delay element can be set by means of a setting signal which can be input via the signal setting input.
Preferably, the settable delay element is formed by at least one capacitor, one of whose electrodes is electrically connected to the oscillator stage output and whose other electrode is electrically connected to a fixed potential. The fixed potential is preferably VSS, i.e. the potential on the integrated circuit which is provided for xe2x80x9cearthingxe2x80x9d. It is further preferred that the settable delay element may comprise a further capacitor, which can be connected in parallel with the first capacitor by means of the setting signal. The delay element duration xcfx84VG can be influenced by the size of the capacitance of the delay element.
It is further preferred that the oscillator stages each comprise an inverting element.
The signal generating device preferably comprises N oscillator stages.
In a preferred embodiment, the following holds true for the delay duration xcex94T=1/(2xc2x7Nxc2x7f), and the following preferably holds true for the signal S1(t)=SN(txe2x88x92xcex94T)xe2x88x92k1/(2f)), where k1 xcex5{0; 1}. Preferably, k1=1.
It is thus particularly preferred that the first signal S1 again follows the last signal SN and the same delay duration is provided between all the signals.
The invention furthermore provides an integrated circuit which comprises a signal generating device according to the present invention or a preferred embodiment thereof.